Computing circuitry

ABSTRACT

This application relates to computing circuitry, and in particular to analogue computing circuitry suitable for neuromorphic computing. An analogue computation unit for processing data is supplied with a first voltage from a voltage regulator which is operable in a sequence of phases to cyclically regulate the first voltage. A controller is configured to control operation of the voltage regulator and/or the analogue computation unit, such that the analogue computation unit processes data during a plurality of compute periods that avoid times at which the voltage regulator undergoes a phase transition which is one of a predefined set of phase transitions between defined phases in said sequence of phases. This avoids performing computation operations during a phase transition of the voltage regulator that could result in a transient or disturbance in the first voltage, which could adversely affect the computing.

The present disclosure is a continuation of U.S. Non-Provisional patentapplication Ser. No. 16/859,298, filed Apr. 27, 2020, which claimspriority to U.S. Provisional Patent Application No. 62/844,339, filedMay 7, 2019, and United Kingdom Patent Application No. 1909971.2, filedJul. 11, 2019, each of which is incorporated by reference herein in itsentirety.

FIELD OF DISCLOSURE

This field of representative embodiments of this disclosure relates tomethods, apparatus and/or implementations concerning or relating tocomputing circuitry, and in particular to methods and apparatus foroperation and power management for computing circuitry.

BACKGROUND

Artificial neural networks (ANNs) are increasingly being proposed foruse in a number of different areas, e.g. for classification orrecognition purposes. An ANN typically comprises a number of processingnodes or artificial neurons. Each processing node can receive aplurality of data inputs and generate an output based on a weightedcombination of the data inputs and a transfer function. Typically theprocessing nodes may be arranged in layers and the output of aprocessing node of one layer may be provided to one or more processingnodes of a succeeding layer.

In order to perform a particular task, the ANN is trained using atraining data set during a learning or training stage, where trainingdata is supplied to the ANN, and weightings, applied by individualneurons or nodes of the network to their inputs, are adjusted based onthe task being performed. By comparing the resultant outputs with theknown training data set, and repeating them over a series of iterations,the neural network learns what are the optimum weighting factor valuesto apply to the inputs. The goal is to determine a set of overallweights such that input data that is known to correspond to a particulardefined class is correctly identified as belonging to that class andinput data known not to correspond to that defined class is notincorrectly identified as such. The training stage requires asignificant amount of processing to accurately determine the bestweights to use for the task being performed. The ANN is thus typicallytrained in a centralised way in a suitable computing facility, e.g. ahigh performance server or the like.

Once trained, the ANN can be used during an inference process with newlyacquired data, e.g. for classification or recognition purposes. Thelearned weights may be supplied together with an inference engine orsystem, which is subsequently arranged to receive operational data andfor the constituent neurons to apply the programmed weights to theirdata inputs and provide the system outputs.

In at least some approaches, the inference stage is performed bycentralised servers or “in the cloud”, i.e. the trained ANN may behosted on a centrally accessible computing facility and may receive datainputs from remote devices, such as so-called “edge” devices, e.g.mobile phones, tablet computers, “smart” devices, etc. For example, toallow for a user of a device such as a smartphone to instruct internetsearch queries by voice, the speech of the user could be captured by thesmartphone and the relevant audio transmitted, possibly after someinitial processing to extract features of interest, to an ANN trainedfor speech recognition which is hosted on a data centre. The ANN canthen perform inference on the received audio.

However, in at least some instances, it may be desirable to implementthe ANN for inference locally, i.e. in the edge device operated by theuser.

Processing data using a trained ANN, i.e. performing inference, mayinvolve significant computation. For an ANN, the input to eachprocessing node is a typically a vector of input variables, and theinput vector may have a relatively large number of elements. For atleast some ANNs the processing in each processing node effectivelyinvolves multiplying the input vector by a matrix of stored weights andthen combining the processed results into an output vector. The matrixof stored weights may have a large number of elements, which need to bestored in memory, and the matrix multiplication will involve a largenumber of calculations. Implementing a trained ANN with a digitalprocessor based on the Von Neumann architecture would involve the weightvalues being stored in memory. Performing the computation associatedwith operating the ANN for inference would thus involve a large numberof individual calculations, with memory reads to retrieve the relevantweight value and memory writes to store the result of the individualcalculations. The computation would, in general be sequential in eachprocessor core. This means that there may be some computational latencyassociated with performing the computations necessary for operating theANN. In some applications, for instance for voice recognition, suchlatency may be undesirable.

Additionally, especially for portable devices, low power consumption isgenerally desirable. This is particularly the case where the computingmay be performed as part of some function that is provided relativelycontinuously over a long timescale. For example it may be desirable toallow for an electronic device to be operable in a mode to respond tovoice commands issued at any time, without requiring the user tophysically interact with the device in any way beforehand. Such“always-on” functionality requires a microphone of the device to beactive and for audio detected by the microphone to be analysed, in asubstantially continuous manner, to detect any voice activity. Theanalysis may involve at least some processing of the audio signal whichmay involve significant computation, e.g. inference to detect whether adefined trigger word or phrase was spoken and/or to determine whetherthe voice activity corresponds to a registered user of the device.Implementing such processing using a conventional digital processor mayrequire a digital processing chip to be active relatively continuously,which may result in an undesirable amount of power consumption.

SUMMARY

Embodiments of the present disclosure thus relate to methods, apparatusand systems for computing that at least mitigate at least some of theabove mentioned issues.

Accordingly, in one aspect there is provided computing circuitry,comprising:

-   -   an analogue computation unit for processing data;    -   a voltage regulator configured to supply a first voltage to the        analogue computation unit and operable in a sequence of phases        to cyclically regulate the first voltage; and    -   a controller configured to control operation of the voltage        regulator and/or operation of the analogue computation unit such        that the analogue computation unit processes data during a        plurality of compute periods that avoid times at which the        voltage regulator undergoes a phase transition which is one of a        predefined set of phase transitions between defined phases in        the sequence of phases.

The controller may, in some examples, be configured to control operationof the analogue computation unit to suspend the analogue computationunit from processing data during a period where the voltage regulator isundergoing one of the phase transitions in the predefined set. Thecontroller may be configured to control operation of the analoguecomputation unit to start and end a compute period during at least onephase of the sequence of phases. In some examples the controller may beconfigured to control operation of the analogue computation unit tostart and end a compute period during each one of the sequence ofphases. In some examples however the controller may be configured tocontrol operation of the analogue computation unit so that there are nocompute periods when the voltage regulator is in at least one predefinedphase of the sequence of phases.

In some examples the predefined set of phase transitions may compriseall of the phase transitions between phases in the sequence of phases.In other examples the predefined set of phase transitions may notcomprise all of the phase transitions between phases in said sequence ofphases. In which case, the controller may be configured to controloperation of the analogue computation such that at least one computeperiod extends over a period that includes a phase transition which isnot one of the predefined set of phase transitions.

In some examples the controller may be configured to control the voltageregulator so as to suspend the voltage regulator from undergoing a phasetransition in the predefined set of phase transitions so as to allowtime for a compute period to be completed. The analogue computation unitmay be configured to provide a computation status to the controller,indicative of whether computing may be suspended, and the controller maybe configured to control operation of the voltage regulator based, atleast partly, on the computation status.

In some examples the voltage regulator may be configured to provide aregulator status to the controller, indicative that the voltageregulator is undergoing or is about to undergo a phase transition in thepredefined set of phase transitions, and the controller is configured tocontrol the operation of the voltage regulator and/or the operation ofthe analogue computing unit based, at least partly, on said regulatorstatus.

In some examples the controller may comprise a clocking unit configuredto supply a first clock reference signal to the voltage regulator tooperate the voltage regulator to cycle through the plurality of phases.The controller may be configured to operate the clocking unit tomaintain the first clock reference signal at a constant signal level tosuspend the voltage regulator from undergoing a phase transition.

In some examples the controller may be configured to control the voltageregulator to operate in a first mode to cyclically regulate the firstvoltage and in a second mode to suspend regulation of the first voltage.The controller may be further configured to control the analoguecomputing unit so that at least some compute periods occur when thevoltage regulator is operating in the second mode. In examples where thecontroller includes a clocking unit, the controller may, in the secondmode, operate the clocking unit to maintain the first clock referencesignal provided to the voltage regulator at a constant signal level.

The controller may be configured to repeatedly control operation of thevoltage regulator in the first mode during a plurality of first timeperiods, interspersed with operation of the voltage regulator in thesecond mode during a plurality of second time periods. The duration ofthe first time periods and the second time periods may, in someexamples, be predefined. In some examples the duration of at least oneof the first time periods and the second time periods is variable. Inthe first mode of operation of the voltage regulator, the controller maybe configured to compare an indication of the magnitude of the firstvoltage to a first threshold and to switch to the second mode if theindication of the magnitude of the first voltage crosses the firstthreshold. Additionally or alternatively, in the second mode ofoperation of the voltage regulator, the controller may be configured tocompare an indication of the magnitude of the first voltage to a secondthreshold and to switch to the first mode if the indication of themagnitude of the first voltage crosses the second threshold value. Thefirst threshold value and the second threshold value may be predefined,or at least one of the first threshold value and the second thresholdvalue may be selectively variable.

The controller may be configured to control the analogue computing unitsuch that there is a first compute period during a period of operationof the voltage regulator in the second mode and a second compute periodduring a subsequent period of operation of the voltage regulator in thesecond mode, wherein the first and second compute periods areinterspersed with at least one period of operation of the voltageregulator in the first mode.

In some examples the analogue computation unit may comprise acompensation module configured to apply a compensation for voltage droopbased on an indication of the magnitude of the first voltage.

The analogue computation unit may comprise at least one processing blockfor producing an output signal, in which case the compensation modulemay be configured to apply the compensation to the output signal fromsaid processing block. The output signal from the processing block may,in some examples, be an analogue output signal. The analogue computationunit may comprise at least one analogue-to-digital converter configuredto convert said analogue output signal to a digital output signal; and,in some examples, the compensation to the output signal may comprise aconversion gain for the analogue-to-digital converter.

The analogue computation unit may comprise at least a first processingmodule and a second processing module. In some examples the controlleris configured to control the first processing module to process data andto control the second processing module to suspend processing of dataduring a first compute period, and to control the first processingmodule to suspend processing of data and to control the secondprocessing module to process data during a second, different, computeperiod.

The voltage regulator may, in some implementations, comprises an inputto receive a voltage from a battery.

The voltage regulator may comprise at least one of: a DC-DC converter; acharge pump; or a buck or boost converter.

The first voltage may comprise a supply voltage to power the analoguecomputation unit.

In some examples the analogue computation unit is configured to receivean input data signal vector and to perform a multiplication of the datasignal vector by a matrix of weight values. In some examples theanalogue computation unit may comprise at least part of an inferencecircuit for an artificial neural network.

The computing circuitry may be implemented as an integrated circuit.

Aspects also relate to a computing device comprising the computingcircuitry of any of the variants as described herein. The computingdevice may be at least one of: a battery powered device; a portabledevice; a communications device; a smartphone; a computing device; alaptop, notebook or tablet computing device; a wearable device; asmartwatch; a voice controlled or activated device; a smart speaker; adomestic appliance.

In another aspect there is provided computing circuitry, comprising:

-   -   an analogue computation unit for processing data;    -   a voltage regulator configured to supply a first voltage to the        analogue computation unit and operable in a first mode in a        cyclic sequence of phases to regulate the first voltage; and    -   a controller configured to control the analogue computation unit        and/or the voltage regulator so that data processing is        performed during a period that does not include any instance of        a predefined set of phase transitions of the voltage regulator        between defined phases in said sequence of phases and that data        processing is suspended during any period that includes an        instance of said predefined set of phase transitions.

Unless expressly indicated to the contrary, any of the various featuresof the various implementations discussed herein may be implementedtogether with any one or more of the other described features in any andall suitable combinations.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of examples of the present disclosure, and toshow more clearly how the examples may be carried into effect, referencewill now be made, by way of example only, to the following drawings inwhich:

FIG. 1 illustrates two examples of circuitry for analogue computing;

FIG. 2 illustrates one example of computing circuitry according to anembodiment;

FIGS. 3 a, 3 b and 3 c illustrate an example two-phase charge pump andmethod of operation;

FIGS. 4 a, 4 b and 4 c illustrate example of timing diagrams forwaveforms of computing circuitry according to embodiments;

FIG. 5 illustrates another example of a timing diagram for waveforms ofcomputing circuitry according to embodiments;

FIGS. 6 a, 6 b and 6 c illustrate more examples of timing diagrams forwaveforms of computing circuitry according to embodiments;

FIG. 7 illustrates one example of an analogue computing array;

FIG. 8 illustrates a computation unit with two processing modules;

FIGS. 9 a and 9 b illustrate further examples of timing diagrams forwaveforms that may be suitable for the computing unit of FIG. 8 ;

FIG. 10 illustrates an analogue computing unit with compensation forvoltage droop;

FIG. 11 illustrates an example flowchart of a method of operatingcomputing; and

FIG. 12 illustrates an example of an electronic device with analoguecomputing circuitry.

DETAILED DESCRIPTION

The description below sets forth example embodiments according to thisdisclosure. Further example embodiments and implementations will beapparent to those having ordinary skill in the art. Further, thosehaving ordinary skill in the art will recognize that various equivalenttechniques may be applied in lieu of, or in conjunction with, theembodiments discussed below, and all such equivalents should be deemedas being encompassed by the present disclosure.

As noted above performing inference using an artificial neural network(ANN) is one example of an application that may involve significantcomputation, for instance matrix multiplication, during operation and,for which, conventional digital processing based on the Von Neumannarchitecture may have disadvantages in terms of processing throughputand/or power consumption.

It has been proposed that at least some of the computation associatedwith an ANN may be implemented using computing circuitry where computingis performed, at least partly, in the analogue domain. For instance,neuromorphic computing may use at least some analogue or mixed-signalcircuitry that can implement a model of a neural system, e.g. an ANN.Neuromorphic computing circuitry has been proposed. Computing in theanalogue domain, or analogue computing, may involve processing datavalues where at least some data values are represented by the analoguevalues of some electrical property, e.g. instantaneous voltage orcurrent, or possibly average values of voltage or current over a definedtime period.

For example, FIG. 1 illustrates just two examples of circuitry forgenerating an output indicative of the product of a first value, say aninput data value D1, and a second value, say a weight value W1.

In the example circuit 100 a, the input data value D1 may, for instance,be received as a digital input and converted, by a digital to analogueconverter (DAC) 101, to an analogue value A1 a which is supplied to acomponent 102 a with a variable resistance or conductance. In someimplementations, the analogue value output from the DAC may be a voltagevalue, i.e. where the voltage level represents the value of the inputdata D1, and the component 102 a may be an element with a programmableresistance, or equivalently a programmable conductance. If the output ofcircuit 100 a were a virtual earth, the current at the output would beproportional to the voltage of the analogue signal A1 a and inverselyproportional to the resistance of component 102 a. Equivalently themagnitude of the output current OUT1 would be proportional to theproduct of the voltage and the conductance of the component 102 a. Theconductance of the component 102 a may thus be controllably programmedto represent a desired weight value W1 and the output signal OUT1 willbe a current signal with a magnitude proportional to D1*W1. Thecomponent 102 a could be any suitable component with a controllablyvariable resistance/conductance. For some analogue computingarrangements the component 102 a could comprise one or more memristors.Memristors are electronic elements that have a variable resistance whichcan be controllably varied and which have some memory such that aparticular resistance state persists in the absence of applied power.The use of memristors can allow the computing circuit 100 a to alsoinclude a memory function, e.g. for non-volatile storage of a weightvalue, which avoids the need for additional memory.

Circuit 100 b shows an alternative arrangement. In this example a weightsignal W1 is used to control transistor 103 to provide an analoguecurrent with a magnitude that depends on the desired weight value. Theweight signal may be maintained, for example, by charging capacitor 104to a desired voltage. The analogue signal A1 a, which in this instancerepresents the weight value, is input to component 102 b which, in thisexample, comprises a switch 105. In this example the component 102 b isthus effectively variable between a very high off-resistance and a lowon-resistance. The switch 105 may be controlled to apply sometime-encoding modulation to the analogue signal Alb based on the inputdata value D1. For instance the switch 105 may be controlled in apulse-width-modulation (PWM) manner such that the switch passes theanalogue signal A1 b to the output for a proportion of a PWM cycleperiod based on the data value D1, and blocks supply of the analoguesignal A1 b during the rest of the PWM cycle period. The result is thatthe output signal OUT1 is a current signal where the average currentover the whole of the cycle period is proportional to the input datavalue D1 and also proportional to the weight value encoded by the weightsignal W1, i.e. the output current is proportional to D1*W1.

It will of course be appreciated that these are just two examples, andthere are many other ways in which analogue computing could beimplemented. For instance, referring to circuit 100 a, the DAC 101 couldin some implementation be a current output DAC for outputting theanalogue signal A1 as a current signal. The DAC 101 could instead bereplaced with a PWM switch arrangement as described with reference tocircuit 100 b. Some implementations may allow at least some parallelprocessing, for instance the analogue signal output from the DAC 101could be applied to a plurality of components 102 a in parallel, eachprogrammed to represent a respective weight value, so as to performparallel computation to provide the product of the same input value witheach of the plurality of respective weight values. Additionally oralternatively, a plurality of circuits such as 100 a or 100 b could bearranged to receive different input data values. The outputs could besummed by combining the output current signals.

It will also be appreciated that some of the values may be quantised,for instance, referring to the example circuit 100 a, there may be alimited number of different values of resistance/conductance that thecomponent 102 a may be programmed to. It will be understood however thatthe overall approach is analogue. As such, the computing circuitry maybe susceptible to manufacturing tolerances and also variations inoperating parameters, such as variations in any supply or referencevoltages. As shown in FIG. 1 , a DAC of circuit 100 a may receive afirst voltage, V_(COMP), e.g. as a supply or reference voltage. Anyvariation in this received voltage V_(COMP) may have an impact on thelevel of the analogue signal A1. Likewise the analogue signal A1generated in circuit 100 b may vary with the received voltage V_(COMP).In particular any transients affecting the power supply could lead toartefacts in the computation.

Embodiments relate to apparatus and methods for computing, in particularfor analogue computing, and to methods and apparatus for computingcircuitry with control of computing periods with respect to operation ofa power supply. Embodiments of the disclosure are suitable for operatinga computing circuit, in particular a computing circuit that forms atleast part of an artificial neural network (ANN) implemented, at leastpartly, in the analogue domain and/or a neuromorphic computing circuit.

FIG. 2 illustrates an example of computing circuitry 200 according to anembodiment. Computing circuitry 200 comprises analogue computation unit210 configured to receive first data D and process the first data D, atleast partly, in the analogue domain. In some embodiments, the firstdata D may comprise a data signal which is a vector of a plurality ofinput variables, e.g. an input vector D_(j) of j input variables. Theanalogue computation unit 210 is configured to process the receivedfirst data with second data. In some embodiments the second data maycomprise a set of weight values, for example a matrix W_(j,k) of j by kweight values.

In some implementations the relevant weight values may be supplied tothe analogue computation unit 210, in use, by a suitable weight signal.In some embodiments however, the analogue computation unit 210 mayinclude a memory functionality for storing the matrix of weight valuesin the absence of applied power, i.e. the analogue computation unit 210may include some non-volatile memory elements such as memristors asdiscussed above. The weight values may therefore be programmed into theanalogue computing unit in a programming step that occurs before theanalogue computing unit 210 is used for processing data, e.g. forinference.

The analogue computation unit 210 processes the first data D with thesecond data W to implement a desired computation and provides an outputsignal OUT_(UN) for the computing unit. In one example the analoguecomputation unit 210 may be configured as a dot product engine toprocess the received first data vector D_(j) by the weight values matrixW_(j,k) and provide an output vector OUT_(k) with k different outputvariables. The individual output variables could be output to providethe output OUT_(UN) in parallel channels and/or in a time divisionmanner. In some embodiments however there may be further processing,e.g. in an ANN implementation the input data variables may each bemultiplied by a respective weight value and the results combined to forma weighted data combination, which is then processed according to somenon-linear function such as an activation function to provide theresultant output variable. In some embodiments the analogue computationunit 210 may comprise at least part of an ANN, e.g. at least part of aninference circuit or inference engine.

The analogue computing circuitry 200 of FIG. 2 also comprises a voltageregulator 220 configured to supply at least a first voltage, V_(COMP),to the analogue computation unit 210. The voltage regulator 220 maycomprise any suitable apparatus, such as a DC-DC converter, forregulating a received input voltage V_(IN) to provide the first voltageC_(COMP). In some embodiments the voltage regulator 220 may comprise acharge pump or an inductor based DC-DC converter such as a buckconverter. For low power operation of the analogue computing unit 210the voltage regulator 220 may regulate the input voltage V_(IN) to alower magnitude voltage V_(COMP) for supply to the analogue computingunit 210.

In some embodiments the input voltage V_(IN) may be received from asuitable power supply, such as, in at least some modes of operation, abattery. In some embodiments, the voltage V_(COMP) supplied to theanalogue computation unit 210 may be a supply voltage for the analoguecomputation unit 210, i.e. to power various components of the analoguecomputation unit 210. In some embodiments the voltage V_(COMP) suppliedto the analogue computation unit 210 may be a reference voltage, forinstance defining the voltage level corresponding to a certain value,e.g. a zero value level or midpoint voltage for bipolar processing. Insome embodiments the voltage regulator 220 may output more than onevoltage to the analogue computing unit 210, e.g. a supply and/or one ormore reference voltages, although only one voltage is shown in FIG. 2for clarity. In any case, as described above, in some embodiments,analogue signals generated as part of the computing performed by theanalogue computation unit 210 may depend, at least partly, on the levelof the voltage V_(COMP) which is supplied to the analogue computationunit 210.

As will be understood by one skilled in the art, DC-DC converters, suchas charge pumps or buck converters or the like, typically operate tocyclically regulate their output voltage. For instance, duringoperation, a charge pump may cycle through a sequence of differentphases. During one or more of these phases a voltage at an outputterminal of the charge pump (i.e. an output voltage of the charge pumpsuch as V_(COMP)) may be maintained solely by a reservoir capacitor ofthe charge pump which was charged in a previous phase. During such aphase, any load current drawn by the load of the charge pump willdeplete the charge of the reservoir capacitor and cause the relevantoutput voltage to droop. During another one or more of these phases avoltage developed within the charge pump may be applied to the outputterminal, which recharges the reservoir capacitor. This cyclicregulation action results in a voltage ripple at the output. As will beexplained in more detail below, such voltage ripple may be undesirablefor analogue computing, and in particular any transients that may occuras a result of the change of phases of the voltage regulator.

To illustrate this principle, FIGS. 3 a, 3 b and 3 c illustrate, insimplistic form, an example operation of a simple two-phase charge pump320, and how a voltage ripple may be generated by the operation of thecharge pump 320. Referring to FIG. 3 a the example two-phase charge pump320 comprises an input to receive an input supply voltage V_(IN) and anoutput to provide an output voltage, e.g. the voltage V_(COMP). Tomaintain the voltage V_(COMP) at the output, a reservoir capacitor isconnected between the output of the charge pump and ground. Charge pump320 further comprises flying capacitor C_(F) and switching matrix 321.Switching matrix 321 is configured to connect flying capacitor C_(F)with the reservoir capacitor C_(R) in a first configuration in a firstphase ϕ₁ and a second configuration in a second phase ϕ₂.

Referring to FIG. 3 b , in the first phase ϕ₁ the switching matrix 321is configured such that the flying capacitor C_(F) is connected inparallel with the reservoir capacitor C_(R) and disconnected from theinput voltage. This results in both capacitors equalising to the samevoltage. In the second phase ϕ₂, the switching matrix 321 is configuredsuch that flying capacitor C_(F) is connected in series with thereservoir capacitor C_(R) between the input node of charge pump 320 andground. In this configuration, the input voltage V_(IN) is dividedbetween the flying capacitor C_(F) and reservoir capacitor C_(R). Byrepeated operation in these states the reservoir capacitor is repeatedlycharged to a voltage equal to V_(IN)/2, which thus provides the outputvoltage V_(COMP).

FIG. 3 c illustrates a timing diagram showing the variations in thevoltages V_(CF) and V_(CR) of the flying capacitor C_(F) and reservoircapacitor C_(R) during operation of the charge pump 320 during the firstand second phases ϕ₁, ϕ₂. At the start of the first phase ϕ₁, the flyingcapacitor C_(F) and reservoir capacitor C_(R) are connected in paralleland thus equalise to the same voltage. Because of the previous instanceof the second phase, the total voltage of the two capacitors is equal tothe input voltage V_(IN) and thus the capacitors each equalise to avoltage V_(IN)/2. However, as discussed above, due to a load currentdrawn by the load of the charge pump 320, the voltage on both flyingcapacitor C_(F) and reservoir capacitor C_(R) will exhibit droop overthe duration of the phase, as both capacitors are connected to theoutput node of the charge pump 320.

At the end of the first phase ϕ₁ the charge pump transitions to thesecond phase ϕ₂, and the input voltage is divided across the twocapacitors. As both the flying capacitor C_(F) and the reservoircapacitor C_(R) will droop by the same amount over the course of thefirst phase, the transition to the second phase will result in a nearstep change in the voltage across both flying capacitor C_(F) andreservoir capacitor C_(R) to V_(IN)/2. Once again, due to the loadcurrent drawn by the load of the charge pump 320, the voltage across thereservoir capacitor C_(R) will droop over the course of the secondphase. However, as the input voltage V_(IN) is divided across the flyingcapacitor C_(F) and reservoir capacitor C_(R) in series, the voltageacross the flying capacitor C_(F) will ramp up at the same rate as thevoltage droop on the reservoir capacitor C_(R).

This variation in the voltages across flying capacitor C_(F) andreservoir capacitor C_(R) during the second phase, again results in astep-like change as the charge pump 320 transitions from the secondphase ϕ₂ to the first phase ϕ₁ and the voltages on the two capacitorsequalize to V_(IN)/2.

This variation in the voltages across the reservoir capacitor C_(R)during the cyclic regulation of the phases of the charge pump 320 isthus seen as a voltage ripple in the output voltage V_(COMP). Inparticular, the step-like changes that may be generated by the chargepump switching from one phase to the next can be seen as relativelysignificant disturbances in the output voltage V_(COMP).

A DC-DC converter such as a buck converter also operates in a cyclicmanner and can also introduce a voltage ripple into the output voltageof the buck converter. Typically a buck converter operates to cyclicallycause the inductor current to ramp up in some states phases and to allowthe inductor current to ramp down in other states phases.

Thus the output from a buck converter or the like also typicallyexhibits a voltage ripple, as switching between different phases canalso introduce a disturbance into the output voltage.

Other operations of a DC-DC converter may additionally or alternativelycause a disturbance in the output voltage from the converter. Forexample, when a transistor switch changes state there may be a gatefeedthrough voltage. Thus any transitions of switches that are connectedor coupled to the output of the DC-DC converter could potentially resultin some transients. These transient voltages due to switching would alsooccur at a phase transition of the DC-DC converter. Even if the switchesconnected to the output do not change state, parasitic capacitance mayalso be present in a DC-DC converter and coupling via the parasiticcapacitance may occur on phase transitions.

In some instances, the supply voltage V_(IN) provided to the DC-DCconverter may include some relatively high frequency supply noise. Forsome DC-DC converters, in some phases of operation, the supply voltagemay be coupled to the output of the DC-DC converter, i.e. a conductivepath between the input and output via some components is established(such as in phase ϕ₂ illustrated in FIG. 3 b ) and as such, the highfrequency supply voltage noise mat couple to and cause a disturbance inthe output voltage. Referring again to FIG. 2 , if the voltage V_(COMP)supplied to the analogue computing unit 210 by the voltage regulator 220exhibits a disturbance, such as that introduced by any of the processesoutlined above, this could potentially impact adversely on theprocessing performed by the analogue computing unit 210.

The analogue computing circuitry 200 illustrated in FIG. 2 thus furthercomprises a controller 230 which is configured to control operation ofthe voltage regulator 220. The controller 230 is further configured tocontrol the analogue computation unit 210. The controller is configuredto control operation of the voltage regulator 220 and/or operation ofthe analogue computation unit 210 such that the analogue computationunit processes data during a plurality of compute periods so that thecompute periods avoid times at which the voltage regulator undergoes aphase transition which may be expected to result in a disturbance in thevoltage V_(COMP). As discussed above such a phase transition that mayresult in a disturbance in the voltage V_(COMP) may, in particular, beone in which the output of voltage regulator 220 is connected in adifferent configuration that may result in a transient at the output,for instance due to some component being connected to the output duringthe phase transition. Based on the type of voltage regulator it may bepossible to identify a predefined set of phase transitions, i.e.transition between defined phases in said sequence of phases such astransition from a first phase to a second phase etc., that may be likelyto lead to a relatively significant disturbance on the voltage output.As such, the controller 230 operates the analogue computation unit 210to avoid processing data during periods that include a phase transitionfrom said predefined set where a disturbance is expected to result involtage V_(COMP), as a disturbance in the voltage V_(COMP) may adverselyimpact the computation of analogue computation unit 210. The controller230 may therefore be configured to control the timing of the computeperiods with respect to the phases of operation of the voltageregulator, i.e. to control the times at which the compute periods beginand end and/or the times at which the voltage regulator may undergo aphase transitions, to avoid any phase transitions of the predefined setduring a compute period. In some embodiments all of the phasetransitions that occur as part of the sequence may be identified as partof the predefined set, but for voltage regulator only some phasetransitions may be problematic and identified as part of the predefinedset.

Referring to FIG. 2 , the controller 230 may therefore be configured tosupply a regulator control signal EN_(R) to control operation of thevoltage regulator unit 220, e.g. to enable regulation of V_(COMP), andsupply a compute control signal EN_(C) to control operation of theanalogue computation unit 210, e.g. to enable and disable dataprocessing. In one embodiment, controller 230 may comprise a clockingunit 231. In some embodiments, the regulator control signal EN_(R) andthe compute control signal EN_(C) may therefore each comprise a clockreference signal supplied by clocking unit 231.

FIG. 4 a illustrates a timing diagram showing an example operation ofthe controller 230 for generating regulator control signal EN_(R) andcompute control signal EN_(C). As illustrated, regulator control signalEN_(R) may comprise a clock reference signal, which may be supplied fromclocking unit 231, which cyclically controls regulation of the voltageV_(COMP). In some embodiments regulator control signal EN_(R) mayinstead be a non-clock signal which is used to gate clocks orclock-based signals within the regulator.

In the illustrated embodiment, the voltage regulator 220 may comprise aDC-DC converter, which may operate in two-phases of operation. Forexample, the voltage regulator 220 may operate in a similar way to thecharge pump 320 discussed in relation to FIG. 3 a-c . It will beunderstood however that this is just one simple example for the purposesof explanation, and other DC-DC converters could be used, such as chargepumps that operate with more than two different phases and/or whichgenerate different ratios of output voltage to the input voltage. Asdiscussed above a disturbance in the voltage V_(COMP) may, for at leastsome voltage regulators, be likely to occur at every phase transition ofthe voltage regulator 220, i.e. every phase transition of the sequencemay form part of the predefined set of potentially problematic phasetransitions. The controller 230 may therefore control analoguecomputation unit 210 to avoid processing data during every phasetransition of voltage regulator 220, i.e. to time the compute periods toavoid every phase transition.

Referring to FIG. 4 a , the controller may supply a regulator controlsignal EN_(R) as a clock signal for controlling transition between thedifferent regulator phases. In the example of FIG. 4 a , the voltageregulator is configured to transition from the first phase ϕ₁ to thesecond phase ϕ₂, or vice versa, at a rising edge of the regulatorcontrol signal EN_(R). The duration of the regulator phases is thuscontrolled by the cycle period of the regulator control signal EN_(R).The controller 230 may supply the compute control signal EN_(C) toanalogue computation unit 210 to enable the analogue computation unit210 to process data during the period of each regulator phase. However,to avoid any possible disturbance on V_(COMP) due to the phasetransitions of voltage regulator 220, the controller 230 controls thecompute control signal EN_(C) to effectively disable computation duringthe phase transitions of voltage regulator 220. This operation ofcompute control signal EN_(C) suspends the analogue computation unit 210from processing data during a period 401 including the phase transition,in other words the compute period occurs within the duration of a singlephase. Thus any disturbance occurring on voltage V_(COMP) as a result ofthe phase transition does not interact with the processing of data bythe analogue computation unit 210. As, in this example, the controller230 generates the regulator control signal EN_(R) as a clock signal forcontrolling the timing of the phase transitions of the voltageregulator, the controller can readily determine when the phasetransitions will occur and thus can control the compute control signalEN_(C) accordingly. For example the controller could generate or receivea suitable clock signal and apply a small delay. The delayed versioncould be output as the regulator control signal EN_(R) and the undelayedversion used as a look-ahead for controlling the compute control signalEN_(C).

It will be understood that during the compute period within a givenphase of the voltage regulator during which computing is enabled, thevoltage V_(COMP) from the voltage regulator may vary and in particular,in at least some phases, may exhibit some droop as described above.However the voltage change due to such droop may be relatively slow andcontinuous and thus may be less problematic for the analogue computingunit. Additionally and alternatively in some embodiments somecompensation may be applied for this relatively slow droop as will bedescribed in more detail later.

In some embodiments the compute control signal EN_(C) may be a two levelsignal, where one signal level enables computation and the other signallevel suspends or disables computation, as illustrated by the solid linein the example of FIG. 4 a where the signal goes high to start a computeperiod and enable computing and goes low to end the compute period anddisable computing. Alternatively the compute control signal EN_(C) mayitself comprise a clock signal for controlling operation of the analoguecomputation unit 210. For instance the analogue computation unit 210 mayprocess data in a computing cycle defined by a clock signal, e.g. by therising edge of a clock signal. The processing period may have a shorterduration than the period of a phase of the voltage regulator so that oneor more processing periods may be completed within a single phase of thevoltage regulator. In this case, as illustrated by the dotted waveformin FIG. 4 a , the compute control signal EN_(C) could be a clock signalwhich is supplied to enable one or more processing cycles in a computeperiod during each phase of the voltage regulator, but which issuspended during the period 401 including a phase transition so as toavoid any computing being performed at the point of the phase transitionof the voltage regulator 220.

In the example of FIG. 4 a , the compute control signal EN_(C) iscontrolled so as to disable or suspend computing for each phasetransition of the voltage regulator, which thus mitigates the risk ofany transients resulting from a phase transition affecting thecomputing. In some instance however the voltage regulator 220 may be aDC-DC converter for which at least one of the phase transitions of thevoltage regulator 220 may not be expected to cause any significantdisturbance in the voltage V_(COMP) output from the regulator 220. Inother words at least one phase transition in the sequence of phases maynot form part of the predefined set of potentially problematic phasetransitions. In which case the controller may be configured so as toallow computing to continue during such a phase transition, such asillustrated in FIG. 4 b.

FIG. 4 b thus illustrates a timing diagram showing another exampleoperation of the controller 230 for generating regulator control signalEN_(R) and compute control signal EN_(C). The controller 230 may againgenerate regulator control signal EN_(R) and compute control signalEN_(C) as described in a similar way to that described with reference toFIG. 4 a . However, in the illustrated embodiment of FIG. 4 b , thevoltage regulator 220 is configured to transition through three phasesϕ₁, ϕ₂, ϕ₃.

The phase transition from the first phase ϕ₁ to the second phase ϕ₂, maybe one which is expected to cause a disturbance in the voltage V_(COMP),and thus forms part of the predefined set of phase transitions to beavoided for computing. For example, for a charge pump the transitionfrom the first phase ϕ₁ to the second phase ϕ₂, may result in adifferent capacitance being connected to the output which could resultin a step change in voltage of the output, and/or a switch transition ofa switch connected to the output and hence the possibility of a gatevoltage feedthrough transient. As such, the controller 230 may thereforecontrol compute control signal EN_(C) so that the compute period avoidsthis phase transition, i.e. to disable or suspend the analogue computingunit 210 from processing data during a period 401 including this phasetransition. However, during the phase transition from the second phaseϕ₂ to third phase ϕ₃, the voltage V_(COMP) may be not expected toexperience any significant disturbance and such a phase transition maythus not form part of the predefined set of phase transitions to beavoided. For example in the transition from the second to the thirdphase it may be the case that there is no change in the configuration ofcomponents connected to the output. For instance, in the second phasethe relevant output of the charge pump may be disconnected from most ofthe rest of the charge pump, with the voltage at the output beingmaintained by the reservoir capacitor. In the third phase, whilstanother part of the charge pump may be reconfigured, there may be nochange in configuration of the output, i.e. the components andconductive paths connected to the output may not change. In which caseit may that no significant disturbance at the output is likely. In someinstances the output configuration could change from the second to thethird phase, but only by the disconnection of some component, e.g. aflying capacitor, in a way that may not result in any significantdisturbance. The controller 230 may therefore control the computecontrol signal EN_(C) during this transition to allow the analoguecomputing unit 210 to continue to process data and the compute periodthus includes this phase transition. As a disturbance is not expected tooccur during the transition from the second phase ϕ₂ to third phase ϕ₃,there may be low risk of any adverse effects on data processingresulting from the voltage V_(COMP) being supplied to the analoguecomputation unit 210 during this transition.

In the examples illustrated in FIGS. 4 a and 4 b , the compute controlsignal EN_(C) is controlled to allow computing during at least part ofeach phase of the voltage regulator, with computing being suspended forat least some phase transitions. In some implementations however it maybe advantageous to suspend computation for the whole of some of theregulator phases, in other words it may be desirable for there to be nocompute periods when the voltage regulator is in at least one predefinedphase of the sequence of phases. For example, in some embodiments, thesupply voltage input to voltage regulator 220 may comprise relativelyhigh frequency noise. In any phase where the input is coupled via aconductive path to the output of the regulator 220, the high frequencysupply noise may result in corresponding noise in the voltage V_(COMP).To mitigate against the presence of such noise adversely affecting thecomputation, the controller 230 may control the analogue computationunit 210 to suspend processing data during a period in which the voltageregulator 220 is operating in a phase where the input of the regulator220 is coupled to the output of the regulator 220, as illustrated inFIG. 4 c.

FIG. 4 c illustrates a timing diagram showing another example operationof the controller 230 for generating regulator control signal EN_(R) andcompute control signal EN_(C). The controller 230 may again generateregulator control signal EN_(R) and compute control signal EN_(C) in asimilar way to that described with reference to FIG. 4 a.

In this example the voltage regulator 220 may comprise two phases ofoperation. In the first phase ϕ₁, the input of the voltage regulator maybe connected to the output of the voltage regulator 220, typically viaone or more components depending on the type of voltage regulator. Asnoted above the supply voltage provided to the voltage regulator 220 maycomprise a noise component, which may manifest itself in the voltageV_(COMP) during the first phase ϕ₁. As such, the controller 230 mayconfigure compute control signal EN_(C) to suspend processing data, sothat there is no compute period, during the entirety of the first phase.This operation may ensure that the disturbance on the voltage V_(COMP)does not cause any adverse effects in the processing of data during thefirst phase ϕ₁.

In the second phase ϕ₂, the regulator 220 may be configured such thatthe input of the regulator 220 is not coupled to the output of theregulator 220. Therefore, during the second phase ϕ₂ the noise componentof the supply voltage input to the regulator 220 may not cause anydisturbance of the voltage V_(COMP). The analogue computation unit 210may thus be able to process data without the voltage V_(COMP) causingany adverse effects on data processing. The controller 230 may thereforecontrol the compute control signal EN_(C) to enable the analoguecomputation unit 210 to process data during the second phase ϕ₂. Thecompute control signal EN_(C) may however only enable computation ashort time after the transition to the second phase so as to avoid anytransients that may occur with the transition between phases.

In the examples discussed above the regulation control signal EN_(R)comprises a clock signal for controlling the timing of the phases of thevoltage regulator and the controller 230 controls the compute controlsignal EN_(C) with respect to this timing signal so as to enable anddisable computing within periods defined by this clock signal for thevoltage regulator. In other words the timing of the compute periods ofdata processing is controlled to fit within periods defined by thephases of the voltage regulator. Such operation may be appropriate ifthe computing performed by the analogue computing unit 210 operates inprocessing cycles of a known duration and computing may be suspended atany point. In some implementations however the time taken to complete aparticular processing operation may be variable and/or it may beundesirable to suspend computing at certain points. In such a case thecontroller 230 may be operable to adjust the timing of the phasetransitions of the voltage regulator to avoid unwanted phase transitionswhilst computing is being performed.

Referring again to FIG. 2 , in some embodiments the computation unit 210may thus be configured to supply a computation status S_(COMP) tocontroller 230. Status S_(COMP) may comprise a signal indicative ofwhether or not the analogue computing unit is processing data and/or hascompleted a set of operations and computing may be suspended. In someembodiments, controller 230 may be configured to control operation ofvoltage regulator 220 based on the status S_(COMP) of analoguecomputation unit 210.

In some embodiments, controller 230 may suspend the voltage regulator220 from undergoing a phase transition when the status S_(COMP) of theanalogue computation unit 210 indicates that the analogue computationunit 210 is processing data and computing should not be suspended, so asto avoid a possible disturbance in the voltage V_(COMP). In someembodiments, the controller 230 may therefore control the voltageregulator 220 to delay the phase transition until the status indicatesthat analogue computation unit has finished processing data or completeda processing operation and computing may be suspended.

FIG. 5 illustrates a timing diagram showing an example operation of thecontroller 230 for generating regulator control signal EN_(R) andcompute control signal EN_(C) where the controller 230 may delay a phasetransition of the voltage regulator. The controller 230 may generateregulator control signal EN_(R) and compute control signal EN_(C) in asimilar way as described with reference to FIG. 4 a.

In this example voltage regulator 220 is operable in two phases, firstphase ϕ₁ and second phase ϕ₂. In the illustrated example the controller230 may control the compute control signal EN_(C) so as to disablecomputing during each phase transition of voltage regulator 220, in asimilar way as described with reference to FIG. 4 a . Controller 230 mayfurther be configured to operate voltage regulator 220 such that,nominally, the voltage regulator 220 is operated in first phase ϕ₁ andsecond phase ϕ₂ for an equal duration of time T.

In this example however the controller 230 is further configured tocontrol operation of voltage regulator 220 based on the status S_(COMP)of analogue computation unit 210. Referring to FIG. 5 , in this examplethe voltage regulator is initially operating in the first phase. Aftertransitioning to this phase, the compute control signal enablescomputing and starts a compute period. The analogue computing unit thusstarts computing and generates the computing status signal to indicatecomputing is occurring. In this example the necessary compute operationsare completed within this phase duration T, thus the computing statussignal S_(COMP) changes state to indicate computing can be suspended.The computing control signal EN_(C) thus suspends computing before theend of the phase period so as to suspend computing during a period 501comprising a phase transition. In the next phase, in this example thesecond phase, the compute control signal EN_(C) re-enables computing andthe analogue computing unit 210 starts computing. In this examplehowever the analogue computing unit 210 is still processing an operationor series of operations at the end of the normal phase duration T. Inthis case the computing status signal S_(COMP) indicates that computingshould not be suspended and thus the phase transition is delayed toavoid any transient. When the computing status signal signals that theoperation is complete, the compute control signal indicates any furthercomputing should be suspended and the regulator control signal is thencontrolled to allow the phase transition. The phase transition is thusdelayed by an amount ΔT. In some embodiments the phase transition mayoccur as soon as possible after computing has finished, but in someembodiments the phase transition may occur at the next relevant clockedge of a clock signal used for the regulator control signal.

During the period in which a phase transition is delayed the voltageregulator may persist in its current phase, as illustrated in the FIG. 5. However in some embodiments, the controller 230 may control thevoltage regulator 220 to transition the voltage regulator to a holdingphase, for instance which may correspond to phase in which a reservoircapacitor of the voltage regulator 220 is disconnected from the othercomponents of the voltage regulator 220, such that, voltage V_(COMP) isprovided solely from the reservoir capacitor. Whilst transitioning fromthe present operating phase of the voltage regulator to the holdingphase may involve a phase transition, such a phase transition, wherecomponents are only disconnected from the output, may be one which isunlikely to generate any disturbance on the output. In some embodiments,one of the normal phases of operation of the regulator 220 may besuitable as such a holding phase, and thus the controller may transitionto such a phase, possibly out of sequence when the status signalS_(COMP) indicates that the analogue computing unit 210 is processingdata and a phase transition would normally occur.

The discussion above has focussed on the voltage regulator 220undergoing a phase transition at a time determined by a clock signal(unless the transition is possibly delayed to allow a computingoperation to complete, but even then, as mentioned, the phase transitionmay occur at the next relevant clock edge). In some DC-DC converters,such as some charge pumps for example, each phase transition maynormally be triggered by a clock signal and thus the phase transitionswould be synchronised to the clock signal. In the examples discussedabove the regulator control signal may provide the clock signal forcontrolling the phase transitions, however in some embodiments thevoltage regulator may comprise its own clock generator and the regulatorcontrol signal EN_(R) could be a signal that either enables the voltageregulator to undergo phase transitions or which suspends the voltageregulator from undergoing phase transitions. In which case, thecontroller 230 may need to receive an indication of when the voltageregulator will normally undergo a phase transition so that it can enableor disable computing at an appropriate time.

Also, some voltage regulators 220 may comprise a DC-DC converter whereinat least some phase transitions are not synchronised to a clock signal.For example, a buck converter switches between a first charging phase,in which an inductor node is coupled to the input voltage, and a seconddischarging phase, in which the inductor node is coupled to a referencevoltage such as ground. In some buck converters one of the phasetransitions may be determined by a clock signal, but the other phasetransition may be based on the comparison of a monitored voltage orcurrent to a threshold and the duty cycle of the converter phases mayvary in use to maintain the desired output voltage. For such convertersthe times at which the voltage regulator 220 undergoes at least somephase transitions may not be predetermined and may not be synchronisedto a control clock signal.

Referring again to FIG. 2 , in some embodiments, controller 230 may thusbe configured to receive a regulator status SR from regulator 220. Theregulator status SR may be indicative of which phase the regulator isoperating in and/or may further indicate that the regulator hasundergone or would, in normal operation, be about to undergo, a phasetransition. In embodiments where at least some of the phase transitionsare all controlled by a clock signal which is not supplied by thecontroller 230, the controller could receive a version of the relevantclock signal. In some instances a delayed version of the clock may beused by the voltage regulator to control the phase transitions, with anundelayed version being supplied to the controller 230 to control thecompute control signal in a similar manner as described above so as toprovide advance warning of the phase transition to the controller 230 soit can suspend computing at an appropriate time.

In some embodiments, for phase transitions that are not synchronised toa clock signal, the regulator status SR may be indicative that thevoltage regulator 220 achieving or approaching a condition to undergo aphase transition which is one of the predefined set expected to resultin a disturbance in the voltage V_(COMP). For example, as discussedabove a buck converter may be operable in a first charging phase or asecond discharging phase and at least one phase transition may becontrolled by an internal control unit of the converter and notsynchronised to a clock signal. For such a phase transition theregulator status SR may be output from the control unit. In someembodiments computing may be performed during just one of the phases,which may be the phase which may start at any time during the convertercycle period, but which ends at a time defined by a clock signal. Forexample in a peak-current mode buck converter the first charging phasemay start at a time synchronised to a clock signal and end at a variabletime determined by the control unit. The second discharging phase maythus start at the variable time and finish at a time determined by theclock signal. The controller 230 may be configured to enable computingjust during the second discharging phase so as to avoid the possibilityof any supply noise adversely affecting the computing and/or so that thedischarging phase can be extended if required to complete a computingoperation without any risk of overcharging any voltage components (whichcould be risk with extending the charging phase). In which case theregulator status signal may be an indication that the voltage regulatorhas transitioned from the first charging phase to the second chargingphase and thus computing can be enabled.

Computing can then be suspended at a time based on the clock signal tosuspend computing prior to the transition from the second phase to thefirst phase.

In some embodiments however it may be desirable to perform computingduring a phase in which the end of the phase is not synchronised to aclock signal but the relevant phase transition would be likely to leadto an unwanted disturbance on the voltage V_(COMP) In which case theregulator status signal SR may indicate that the voltage regulator isundergoing or is likely to about to undergo a phase transition such thatthe controller can suspend computing before any disturbance on thevoltage V_(COMP) as a result of the phase transition.

As noted above for some DC-DC converters, the phase transition may betriggered by a monitored signal reaching a first threshold. In someembodiments the regulator status could comprise an indication that thefirst threshold has been reached and that the voltage regulator isundergoing a phase transition. The controller 230 may receive thissignal and suspend computing before the phase transition results in anydisturbance to the voltage V_(COMP) In some embodiments however theremay be some latency associated with the time required to generate thesignal to suspend computing and for any computing cycle to complete, inwhich case advance warning of the transition would be beneficial. Insuch a case the voltage regulator control unit may also compare themonitored signal to a second threshold, which will be reached before thefirst threshold, and which is set at a level to give sufficient time,based on the expected worst case or monitored operating conditions, forthe controller 230 to suspend computing.

If the regulator status SR indicates that the regulator 220 is about toundergo a phase transition and, at the same time, a compute statussignal S_(COMP) indicates that the analogue computation unit 210 isprocessing data, the controller 230 may control voltage regulator 220 todelay a phase transition, and thus maintain the current phase, via theregulator enable signal EN_(R), to prevent the phase transition fromintroducing a disturbance in voltage V_(COMP) whilst analoguecomputation unit 210 is processing data. Once the compute status signalS_(COMP) indicates that the analogue computation unit 210 has completedthe processing operation, the controller 230 may then enable the voltageregulator 220 to undergo the phase transition to the next phase.

It will also be appreciated that maintaining the voltage regulator 220in a given phase for an increased duration of time, may also cause anincreased variation, e.g. droop, of the voltage V_(COMP) The voltageV_(COMP) may therefore droop to a lower magnitude the longer the voltageregulator is maintained in a given phase. However, as the droop may be arelatively predictable phenomenon and may occur with a relatively slowand constant rate, this may be within the accuracy tolerance of theanalogue computing unit 210 and/or may be mitigated for in the design ofanalogue computation unit 210, as will be described in more detailbelow.

The examples discussed above thus enable computing in computing periodsduring at least some phases of operation of the voltage regulator andsuspends computing during a period that includes a transition betweenphase that would likely lead to an unwanted disturbance on thevoltage(s) V_(COMP) supplied from the voltage regulator to the analoguecomputing unit. In some instances there controller may be configured soas to suspend computing during any phase transition. In some embodimentsthe circuitry may also be configured to control the computing that isperformed during the different phases of voltage regulator operation.

For example, the rate of voltage droop may be different in differentregulator phases and the analogue computation unit 210 and voltageregulator 220 may be configured such that processing operations that mayrequire the longest amount of time to complete by analogue computationunit 210 are performed during such regulator phases with the lowest rateof droop. This may mitigate any effect over the whole computing period,and such regulator phases may be extended if required for the longestperiod with the voltage V_(COMP) dropping below some minimum thresholdfor satisfactory operation.

Equally some phases of regulator operation may exhibit faster rates ofdroop, or a greater likelihood of noise in the voltage V_(co)MP Someprocessing operations may be more robust to minor disturbances or noiseon the voltage V_(COMP) than others. The analogue computation unit maytherefore be configured to carry out more highly sensitive processingoperations or operations that require the highest degree of accuracyduring regulator phases with the least voltage droop or lowest noise.

In some embodiments however it may not be desirable or practical tostart and stop the computing processes within the periods of theregulator phases. Therefore, in some embodiments, controller 230 may beconfigured to operate the voltage regulator 220 in a first mode, withactive regulation of the voltage V_(COMP), and in a second mode tosuspend regulation of the voltage V_(COMP). In the first mode thevoltage regulator 220 thus performs cyclic regulation of the voltageV_(COMP), but in the second mode the cyclic regulation is suspended. Thecontroller 230 may be further configured to control the analoguecomputation unit 210 to process data during a compute period in whichthe voltage regulator 220 is operating in the second mode. Thecontroller may thus control the analogue computation unit 210 so as tonot process data during a period in which the voltage regulator 220 isoperating in the first mode. The controller 230 may thus be configuredto supply the regulator control signal EN_(R) to control operation ofthe voltage regulator 220, e.g. to enable and disable cyclic regulation,and supply a compute control signal EN_(C) to control operation of theanalogue computation unit 210, e.g. to disable and enable dataprocessing. In this way, any disturbance that may be present in thevoltage V_(COMP) during regulation may not interact with the processingof analogue computation unit 210.

FIG. 6 a illustrates another example timing diagram of the waveforms forthe voltage V_(COMP), the regulator control signal EN_(R) and thecompute control signal EN_(C). During a first time period T₁, controller230 operates the voltage regulator 220 in the first mode so as toregulate the voltage V_(COMP) by cyclically sequencing the voltageregulator through a plurality of phases. In this example the controller230 outputs regulator control signal EN_(R) in a high state to enableoperation of the voltage regulator 220 in the first mode. In thisexample the regulator control signal EN_(R) thus enables or disablesoperation of the voltage regulator, where the timing of at least some ofthe phase transitions may be determined by a separate clock signal.However it equally would be possible, as described in more detail later,for the regulator control signal EN_(R) to be a varying clock signalfrom clocking unit 231 during the first mode to control sequencing ofthe voltage regulator 220 through the plurality of phases to regulatevoltage V_(COMP), and then to be held at a constant level, with norelevant clock edges, during the second mode.

During the first time period T₁ the voltage V_(COMP) is thereforeactively regulated to a nominal voltage level V_(NOM) by the voltageregulator 220. In relatively steady state operation, as illustrated inFIG. 6 a , the voltage V_(COMP) output from the voltage regulator willthus be maintained at, or about, the nominal voltage level V_(NOM) butwill exhibit a certain voltage ripple V_(RIPPLE) depending on the loadcurrent drawn and the switching frequency of the voltage regulator 220.Note the nominal voltage V_(NOM) is illustrated as a maximum voltage forsimplicity in FIG. 6 a but equally this could be some other level, suchas an average voltage level, depending on the type of voltage regulator.

As noted above, the voltage ripple V_(RIPPLE) exhibited by the voltageV_(COMP) may introduce a disturbance in the analogue computing circuitry200, which may cause artefacts or errors in the processing of analoguecomputation unit 210. As such, the controller 230 is thereforeconfigured to control the analogue computation unit 210 to process dataduring a compute period in which the voltage regulator 220 is operatingin the second mode i.e. when the voltage regulator 220 suspends cyclicregulation of the voltage V_(COMP).

As illustrated in FIG. 6 a , in the second time period T₂, thecontroller 230 switches operation of the voltage regulator 220 to thesecond mode to disable or suspend regulation of the voltage V_(COMP). Inthis example the regulator control signal EN_(R) goes low and is held ata constant level. This suspends regulation of voltage V_(COMP) and asillustrated in FIG. 6 a , the voltage V_(COMP) will droop, based on theloading on the voltage regulator.

In this suspended regulation mode of operation, the voltage rippleV_(RIPPLE) is no longer present in the voltage V_(COMP) supplied to theanalogue computation unit 210. The controller 230 operates analoguecomputation unit 210 to process data during the second time period T₂,whilst regulation of the voltage V_(COMP) has been suspended and thevoltage ripple V_(RIPPLE) is not present. In this example the computecontrol signal EN_(C) goes from low to high to enable processing. Theanalogue computation unit 210 thus receives and processes data andprovides the output signal OUT_(UN) during the second time period T₂.

The analogue computation unit 210 thus operates to process data during acompute period in which the voltage V_(COMP) supplied to the analoguecomputation unit 210 is free from any voltage ripple, and in particularfrom any transients arising from the phase transitions. Whilst thevoltage V_(COMP) supplied to the analogue computation unit 210 maydecrease, i.e. droop, over the second time period, the relatively slowand continuous voltage droop may be less problematic than the cyclicvoltage ripple, that may comprise a rapid voltage change during a phasetransition.

At the end of the second time period T₂, the compute control signalEN_(C) may, in this example, go low, to stop further data processing andthe regulator control signal EN_(R) may re-enable cyclic regulation bythe voltage regulator 220, i.e. control the voltage regulator 220 tooperate in the first mode. The voltage V_(COMP) will thus again beactively regulated to the nominal voltage V_(NOM), although depending onthe duration of the second time period T₂ and the amount of droop, itmay take a few regulator cycles for the voltage V_(COMP) to reach thenominal voltage level.

The first and second time periods T₁ and T₂ of operation of the voltageregulator 220 in the first and second modes are defined, in thisexample, by the regulator control signal EN_(R), which in this examplegoes high to enable active regulation and goes low to suspend regulation(although it will be appreciated the opposite operation could beimplemented). In the example of FIG. 6 a , the compute control signalEN_(C) enables data processing for the entirety of the second timeperiod T₂. In this example the compute control signal EN_(C) enablesdata processing when in the high state, and thus the compute controlsignal EN_(C) can be seen as being the inverse of, or in antiphase with,the regulator control signal EN_(R). It will be appreciated that theregulator control signal EN_(R) could also be used as the computecontrol signal EN_(C) with one state of the regulator control signalEN_(R) enabling active voltage regulation and suspending computation,and the other state suspending voltage regulation and enablingcomputation. In some implementations however the period in which thecompute control signal EN_(C) enables data processing by the analoguecompute unit 210 may start and/or end at a different time to the secondtime period T₂. For instance there may be short delay between a changeof state of the regulator control signal EN_(R) to signal the beginningof the period T₂ and a corresponding change of state of the computecontrol signal EN_(C). Such delay may, for example, allow time foractive regulation to cease and/or dissipation of any transientsassociated with suspending regulation. Additionally or alternatively, achange of state of the compute control signal EN_(C) to end the periodof data processing may occur a short time before a corresponding changeof state of the regulator control signal EN_(R) to re-enable activeregulation, e.g. to allow time for a current processing cycle tocomplete.

In any case the analogue computing circuitry 200 may therefore be seenas being operable in two modes, a first mode where the voltage regulator220 is actively regulating the voltage V_(COMP) and computing issuspended, and a second mode in the cyclic regulation by the voltageregulator 220 is suspended and data processing is performed, possiblywith a transition between the states where both voltage regulation anddata processing is suspended.

It should be noted that whilst data processing by the analogue computingunit 210 may advantageously be suspended during a period in which thevoltage regulator 220 is actively regulating the voltage V_(COMP) itmay, in some implementations, be advantageous to perform some operationof the analogue computing unit 210 during such period, e.g. to performsome preparatory steps prior to a calculation or to maintain arelatively constant operation. In such a case however the data ofinterest may only be processed during a period in which active voltageregulation is suspended and/or only the results of processing during aperiod in which active voltage regulation is suspended may be consideredvalid.

As noted above, in some embodiments, the controller 230 may selectivelysupply the clock signal from the clocking unit 231 so as to enableoperation in the first mode, but suspend supply of the clock signal soas to suspend cyclic regulation and thus control operation in the secondmode, as illustrated in FIG. 3 b . During the first time period T₁ theregulator control signal EN_(R) may thus be derived from the clocksignal from the clocking unit 231 and thus will cycle between differentsignal levels at the clocking frequency. The voltage regulator 220responds to the rising or falling edges of the regulator control signalEN_(R) as an input clock signal and cycles through a sequence of statesto cyclically regulate the voltage V_(COMP). To operate the voltageregulator 220 in the second mode, the regulator control signal EN_(R)may be held at a constant signal level and thus the lack of any risingor falling edges means that the voltage regulator does not cycle throughany states, which suspends regulation of the voltage V_(COMP).

In some embodiments the controller 230 may be configured to operate theanalogue computing circuitry 200 such that there are a plurality ofcompute periods during which active voltage regulation is suspended andduring which data processing is performed, interspersed with periods inwhich data processing is suspended and voltage regulation is enabled.The controller 230 may therefore operate to repeatedly sequence betweenperiods of voltage regulation by voltage regulator unit 220 and periodsof computation by analogue computation unit 210. In some embodiments,the controller 230 may be configured to repeatedly control operation inthe first mode during a plurality of first time periods T₁ interspersedwith operation in the second mode during a plurality of second timeperiods T₂. In the example of FIG. 6 a , the controller may beconfigured to alternate between instances of the first time period T₁and the second time period T₂ in a repeating alternating sequence.

In some embodiments the durations of first time period T₁ and secondtime period T₂ may be predetermined, i.e. in some embodiments thecontroller 230 may be configured to operate the voltage regulator unit220 in the first mode, with data processing by the analogue computingunit 210 suspended, for a predetermined first duration of time andoperate the voltage regulator unit 220 in the second mode, with voltageregulation enabled, for a predetermined second duration of time. In someinstances, the first time period T₁ and the second time period T₂ may beequal in duration. In some instances the first time period T₁ and thesecond time period T₂ may be unequal in duration.

As noted above, during the second time period, where voltage regulationis suspended, but during which the analogue computing unit 210 may beprocessing data, the analogue computing unit 210 may draw current from asuitable reservoir of the voltage regulator, e.g. a reservoir capacitor,and the voltage V_(COMP) may droop. It may be desirable to limit theamount of droop during the second time period and thus the duration ofthe second time period may be determined so as to ensure the voltagedroop during the second time period remains within acceptable limits,even in the worst case expected operating conditions. The duration ofthe second time period may also be determined with regard to theoperation of the analogue computing unit 210, for instance theprocessing may operate in processing cycles of a defined duration and toavoid artefacts it may be desirable to complete a correspondinglydefined number of processing cycles. The duration of the second timeperiod may therefore be set to allow a defined number of processingcycles to be completed during the period in which data processing isenabled.

As also noted above, the voltage droop during the second time period maymean that, when cyclic regulation is restarted, it may take a number ofregulator cycles for the voltage V_(COMP) to return to the nominalvoltage level. The duration of the first time period may therefore beset so as to allow sufficient time for the regulated voltage V_(COMP) toreturn to the nominal voltage level, and possibly stabilise at such alevel, even in the worst case expected operating conditions, beforeanother instance of the second time period, i.e. before another instanceof operation of the voltage regulator in the second mode.

In some embodiments however the duration of at least one of the firsttime periods T₁ and the second time periods T₂ may be variable. Withreference to FIG. 6 c , during the first time period T₁ with thecontroller 230 operating the voltage regulator unit 220 in the firstmode, the controller 230 may be configured to compare an indication ofthe magnitude of the voltage V_(COMP) to a first threshold V_(TH1),which may be a relatively high threshold indicating that the regulatedvoltage V_(COMP) is sufficiently high so as to allow an instance of asecond time period. In some implementations the controller 230 mayswitch the voltage regulator 220 to the second mode if the indication ofthe magnitude of the voltage V_(COMP) crosses the first thresholdV_(TH1). In some examples the controller 230 may therefore receive anindication of the magnitude of the voltage V_(COMP) and compare it to athreshold, or the regulator 220 or analogue compute unit 210 maydetermine if the voltage V_(COMP) is above the threshold and provide asignal to the controller 230. The duration of the first time period T₁,is thus variable based on how long it takes the voltage V_(COMP) toincrease from the level at the start of the first time period to thelevel of the first threshold.

Additionally or alternatively, in some embodiments, when the voltageregulator 220 is operating in the second mode of operation, thecontroller 230 may be configured to compare an indication of themagnitude of the voltage V_(COMP) to a second voltage threshold V_(TH2),and to switch to the first mode if the indication of the magnitude ofthe voltage V_(COMP) crosses the second threshold value V_(TH2). Thesecond threshold may be a lower threshold indicative of a minimumacceptable voltage level for the voltage V_(COMP). As discussed above,the controller 230 may be configured to receive an indication of themagnitude of the voltage V_(COMP) and compare it with the second voltagethreshold V_(TH2). In some implementations, when the comparisonindicates that the magnitude has crossed the second voltage thresholdV_(TH2), the controller 230 may be configured to switch operation of thevoltage regulator 220 from the second mode to the first mode ofoperation. In some instances however the controller 230 may beconfigured so that the analogue computing unit 210 can complete aprocessing cycle before switching to the first mode of operation, andthe second threshold may be set accordingly. Thus the duration of thesecond time period T₂ may be variable based on the rate of droop of thevoltage V_(COMP).

In some embodiments the first voltage threshold value V_(TH1) and thesecond voltage threshold value V_(TH2) may be predefined. In someembodiments however at least one of the first voltage threshold valueVTH, and the second voltage threshold value V_(TH2) may be variable, forexample based on operating conditions such as temperature. Temperaturemay affect the performance of an analogue system in a variety of ways.Therefore the controller 230 may receive a measure of the temperature ofthe analogue computing circuitry 200 and vary at least one of the firstvoltage threshold value VTH, and the second voltage threshold valueV_(TH2) based on this measure.

It will of course be understood that the waveforms illustrated in FIGS.6 a, 6 b and 6 c are for the purposes of explanation only to illustratethe principles of operation and the actual waveforms that would be seenin use may be quite different. For instance the relative durations ofthe first and/or second time periods with respect to the regulationcycle period illustrated in FIG. 6 a or the clock period illustrated inFIG. 6 b may be quite different in practice. Likewise the form of thevoltage ripple and/or the relative magnitude of the voltage ripplecompared to the voltage droop during the second period may quitedifferent in practice.

Some embodiments thus relate to computing circuitry comprising ananalogue computing unit for processing data and a voltage regulator forproviding at least one voltage to the analogue computing unit. Thecomputing circuitry is configured to periodically suspend active voltageregulation by the voltage regulator and to operate the analoguecomputing unit to process data during a period in which active voltageregulation is suspended. This mitigates the risks of a voltage rippleassociated with active voltage regulation from causing artefacts in thedata processing.

The analogue computation unit 210 may comprise a plurality of computingor processing cells and may be configured to perform particularcalculations, for instance to implement a dot product engine. Forexample, FIG. 7 illustrates, in a generalised form, one example of acomputing array 701 which may form at least part of the analoguecomputation unit 210. FIG. 7 illustrates that the array 701 may comprisea plurality of processing cells 702. Each processing cell 702 maycomprise circuitry such as described with reference to FIG. 1 , e.g.circuitry 100 a or 100 b or other similar circuitry. The example arrayof FIG. 7 is formed as a crossbar type array. The array 701 in thisexample has j rows for receiving a data vector with j data variables.The relevant input data for each row is supplied to each of the kprocessing cells 702 of that row. In the example of FIG. 7 the array 701is also arranged in a plurality of columns 703, and the output of eachindividual processing cell 702 in a column is combined to form aweighted data combination. In some implementations the weighted datacombination for each column could be provided as a respective outputvariable, OUT_(C1), of an output vector (e.g. OUT_(UN)), however in someembodiments there may be some additional processing, such as processingaccording to a non-linear function and/or conversion to a digital outputby processing block 704. In some implementations there may be aplurality of such processing arrays 701 and, in some examples, at leastsome processing arrays could be arranged as processing nodes in a seriesof layers such that some processing arrays operate to process data whichis output from one more arrays of a preceding layer.

In some implementations, to process data the analogue computing unit 210is enabled to perform data processing and substantially all of theanalogue computing unit 210 may be activated and used to process data.In some embodiments however the analogue computing unit 210 may comprisea plurality of processing sub-units or modules which may be selectivelyenabled to perform processing and the computing circuitry 200 may beconfigured so that not all of the processing sub-units or modules areused for processing data during a given time period.

For example, FIG. 8 illustrates an example of computing circuitry 200with an analogue computation unit 210 having a plurality of computationsub-units or processing modules 801. FIG. 8 shows just two suchprocessing modules 801 a and 801 b for clarity but it will beappreciated that there may be more processing modules in practice. Eachprocessing module 801 may, for example, comprise a separate processingarray 701 such as illustrated in FIG. 7 .

As noted above, at least some ANNs may be implemented with a pluralityof layers, with a succeeding layer processing data from a precedinglayer. Each layer may require one or more processing arrays. Also, itwill be appreciated that, in practice, a processing array 701 will beimplemented with a fixed number of processing elements, e.g. a fixednumber of rows and columns. This number may be chosen with respect tothe expected size of the weight matrix and input and output vectors.However there may be a practical limit to the number of processingelements in a row or column and it may be the case that, in someinstances it may not be possible to implement a desired calculationusing a single processing array and the calculation may need to be splitover separate processing arrays. In any event, the analogue computingcircuitry 200 may comprise a plurality of processing arrays. It may beadvantageous for the same voltage regulator 220 to regulate and supplyvoltages for multiple different processing arrays, as otherwise eachprocessing array may require its own voltage regulator which mayincrease the size of the circuitry and possibly lead to additionalproblems of mismatch.

In such case, the computing circuitry 200 may be operable such that notall of the processing modules that receive voltages from the samevoltage regulator are enabled for data processing at the same time. FIG.9 a illustrates an example timing diagram that may be implemented foranalogue computing circuitry 200 illustrated in FIG. 8 . FIG. 9 aillustrates that the controller 230 may generate a regulator controlsignal EN_(R) in a similar fashion as described above, but in thisexample the compute control signal EN_(C) comprises separate controlsignals EN_(CA) and EN_(CB) for controlling the first and secondprocessing modules 801 a and 801 b respectively.

As discussed above, the controller 230 may be configured to operate thevoltage regulator 220 in the first mode by cyclically operating thevoltage regulator through a plurality of phases to cyclically regulatethe voltage V_(COMP) during a first time period T₁. Active regulation bythe voltage regulator 220 introduces a voltage ripple V_(RIPPLE) intothe voltage V_(COMP) which could cause errors and artefacts in the dataprocessing of data by the analogue computing unit. Therefore, when thevoltage regulator 220 is operating in the first mode, the controller 230controls both the first processing module 801 a and the secondprocessing module 801 b to disable processing of data.

When there is data to be processed, and the first voltage V_(COMP) issufficiently high, the controller 230 may switch operation of thevoltage regulator 220 to the second mode to suspend active regulation ofthe voltage V_(COMP), and may start a compute period to enable dataprocessing by the analogue compute unit 210. However in the example ofFIG. 9 a the first and second processing modules 801 a and 801 b are notenabled simultaneously.

Thus, during a second time period T₂, with active regulation of thevoltage V_(COMP) suspended, the controller 230 enables the firstprocessing module 801 a to process data, but maintains the secondprocessing module 801 b in the suspended state of operation. In theexample of FIG. 9 a the first compute control signal EN_(CA) thus goeshigh during the second time period T₂, but the second compute enablesignal EN_(CB) remains in the low state.

Separately, during a third time period T₃, with active regulation of thevoltage V_(COMP) suspended, the controller 230 enables the secondprocessing module 801 b to process data whilst operation of the firstprocessing module 801 a is suspended.

Only enabling and operating some of the processing modules at a time (inthis example just one of the processing modules 801 a and 801 b) mayreduce the instantaneous load current drawn by the analogue computingunit at any time, and thus the rate of voltage droop, compared toenabling all of the processing modules (in this example both processingmodules 801 a and 801 b). This may mean that the voltage droop over aprocessing cycle is lower, which may be advantageous in reducing errorsand/or being easier to compensate for, and/or it may allow a longer timefor a computing cycle whilst remaining within an acceptable limit ofdroop.

In some implementations, an instance of the second time period may beimmediately followed by an instance of the third time period. However insuch a case, at the start of the third time period T₃ the voltageV_(COMP) would exhibit the droop that occurred during the second timeperiod T₂. This may still be advantageous as the rate of the change, andoverall magnitude of change, over the third time period may be reducedcompared to both processing modules being enabled at the same time.

However, advantageously the controller 230 may be configured such thatan instance of the second time period T₂ and an instance of the thirdtime period T₃ are interspersed by an additional instance of first timeperiod T₁, during which the voltage regulator 220 actively regulates thevoltage V_(COMP). Thus, in the example illustrated in FIG. 9 a ,following the end of the second time period T₂, active voltageregulation of the voltage V_(COMP) is re-enabled and the voltageregulator 220 may restore the voltage V_(COMP) to the nominal voltagebefore the third time period.

Thus, the controller 230 may be configured to control operation of thevoltage regulator unit in the first mode during a plurality of firsttime periods T₁ interspersed with operation in the second mode during aplurality of compute time periods, e.g. second time period T₂ and thirdtime period T₃. During each of the compute time periods the controller230 may be configured to enable data processing in one or moreprocessing modules but suspend data processing in one or more otherprocessing modules. The controller may be configured to enableprocessing of the processing modules in different computing periodsaccording to some sequence. For instance processing modules associatedwith a layer of an ANN may be enabled in one or more computing periodsbefore enabling processing modules associated with a subsequent layer inone or more subsequent computing periods. In some embodiments thecontroller 230 may be configured to operate such that there is at leastone instance of a first time period T₁ of operation, with active voltageregulation enabled, between successive instances of compute timeperiods, with active voltage regulation suspended.

FIG. 9 b illustrates another example timing diagram that may beimplemented for analogue computing circuitry 200 illustrated in FIG. 8 .In the example of FIG. 9 b , the voltage regulator 220 may comprise atwo-phase DC-DC converter, which may operate in a similar fashion asdescribed above. According to some embodiments, controller 230 mayoperate one of the processing modules of analogue computation unit 210to process data during one phase of operation of voltage regulator 220and operate another one of the processing modules of analoguecomputation unit 210 to process data during another phase of operationof the voltage regulator 220.

In the first period T₁, the voltage regulator 220 may operate in thefirst phase ϕ₁, for a duration corresponding to one clock period of theregulator control signal EN_(R). During the first period T₁, controller230 may operate first processing module 801 a to process data byconfiguring first compute control signal EN_(CA) in the high state. Thecontroller 230 may also suspend the second processing module 801 b fromprocessing data during the first time period by configuring secondcompute control signal EN_(CB) in the low state. As discussed inrelation to FIG. 4 a-c , controller 230 may control analogue computationunit 210 to avoid any data processing during a period in which thevoltage regulator 220 is undergoing a phase transition, due to thevariation in voltage V_(COMP) that can occur during said transitions. Assuch, as the voltage regulator 220 transitions from the first phase ϕ₁to the second phase ϕ₂, controller 230 may suspend first processingmodule 801 a and second processing module 801 b from processing data.

During the second time period T₂ with voltage regulator 220 configuredin the second phase ϕ₂, controller 230 may then operate secondprocessing module 801 b to process data by configuring the secondcompute control signal EN_(CB) in the high state. The controller 230also suspends first processing module 801 a from processing data duringthe second time period T₂ by controlling first compute control signalEN_(CA) in the low state.

Therefore in some embodiments during a period T₁ in which the voltageregulator 220 is operating in a first phase ϕ₁ of a plurality of phases,the controller 230 may be configured to operate the first processingmodule 801 a to process data and to suspend the second processing module801 b from processing data and during a period T₂ in which the voltageregulator 220 is operating in a second phase ϕ₁ of the plurality ofphases the controller 230 may be configured to operate the secondprocessing module 801 b to process data and to suspend the firstprocessing module 801 a from processing data.

It should be noted that the discussion above has focused on processingmodules 801 such as different processing arrays. In some embodimentshowever different processing modules could comprise different parts ofthe same processing array. For example referring back to FIG. 7 , insome implementations it may be possible to operate the variousprocessing cells in one or more columns 703 of the array separately fromother columns of the array. In some implementations this may allowvarious components to be shared between the various columns in atime-division manner, which may be advantageous in terms of size andconsistency. In such a case a processing module could comprise one ormore, but not all, columns of the array, i.e. a subset of the array.More generally a processing module may be implemented by any group ofprocessing circuitry which can be operated separately by another group.

As discussed above, by periodically operating the voltage regulator 220in the second mode of operation, with active cyclic regulation of thevoltage V_(COMP) suspended, and operating, at least part of, theanalogue computing unit 210 to perform data processing during a periodin which voltage regulation is suspended, the problem of voltage ripplecausing artefacts in the processing may be avoided. However the voltagedroop that occurs when the voltage V_(COMP) is not being activelyregulated may result in errors in the processing, for instance in someimplementations the voltage droop may result in a variation in gain.Similarly, operating the voltage regulator 220 to suspend regulation ofthe voltage V_(COMP) and maintaining the voltage regulator 220 in onephase of operation, for the analogue computation unit 210 to complete aprocessing operation, such as that described in relation to FIG. 5 , mayalso result in an excessive droop which may cause errors in processing.In some embodiments the computing circuitry may be configured to atleast partly compensate or correct for the voltage droop that occurs. Insome embodiments the computing circuitry may therefore comprise acorrection or compensation module.

FIG. 10 illustrates an example of computation circuitry 200 according toan embodiment. The computing circuitry 200 comprises an analoguecomputation unit 210 such as described above, but in this example theanalogue computation unit 210 includes a correction module 1001 forapplying a correction due to voltage droop on the voltage V_(COMP).

In the example of FIG. 10 the correction is applied to the output of aprocessing block 1002, where the output of the processing block isproportional to the voltage V_(COMP). For example, referring back toFIG. 1 and the discussion thereof, it will be understood that theprocessing circuitry illustrated will generate an output signal which isa current signal with an average magnitude proportional to the inputdata value D1 and the relevant weight value W1, however the outputcurrent may also be proportional to the voltage V_(COMP). Any variationin the voltage V_(COMP) will thus appear as a gain variation affectingthe output signal. Referring to FIG. 7 , it will be understood that theoutputs of a plurality of processing cells may be combined together, forinstance FIG. 7 illustrates that the outputs from a column 703 ofprocessing cells 702 may be combined. If each processing cell 702 in thecolumn has the same general structure and receives the same voltageV_(COMP) (not illustrated in FIG. 10 ) the combined output will alsothus be proportional to the voltage V_(COMP). In some instancestherefore the processing block 1002 to which compensation is applied maybe group of processing cells whose analogue outputs are combined to forma combined output OUT_(C1).

In such an implementation, as a variation in the voltage V_(COMP)manifests as a gain change, a correction may be applied by varying again applied by an element 1003 having a variable gain. The correctionmodule 1001 may thus receive an indication of the voltage V_(COMP) andgenerate a suitable gain control signal S_(G) for controlling the gainof the variable gain element 1003, so as to provide a corrected outputOUT_(COR).

In some embodiments the processing block 1002 may output a digitaloutput signal, e.g. referring back to FIG. 7 the output of a column 703of processing cells 702 may be converted to digital by processing block704. In which case the variable gain element 1003 may be a digital gainelement and the correction module 1001 may determine a suitable gainvalue to be applied based on the voltage V_(COMP). In some embodimentshowever the output of processing block 1002 may be an analogue signaland the gain element may be an element for applying a variable gain to areceived analogue input.

In some implementations the gain element 1003 may be ananalogue-to-digital converter (ADC). The voltage V_(COMP) may be used todefine a reference for the ADC 1003, for example the correction module1001 may simply be an element with a defined resistance or conductance,so that the gain control signal S_(G) is a current reference that varieswith V_(COMP) in a similar fashion to the output of the processing block1002. The ADC 1003 may convert the output OUT from the processing block1002, based on the reference current S_(G), to provide a digital outputOUT_(COR) which is substantially corrected from any variation inV_(COMP).

In some embodiments the gain element 1003 may comprise an ADC comprisinga PWM encoder. The gain may therefore be adjusted so as to beproportional to the variation in the voltage V_(COMP) by adjusting thecycle period of the PWM encoder, for example by suitably adjusting theramp rate or amplitude of a reference waveform within the PWM encoder.

In some embodiments the gain element 1003 may comprise a function unitfor applying a desired function e.g. a non-linear activation function,to the output of the processing block. As one skilled in the art will befamiliar with, an ANN may be capable of computing linearly non-separablefunctions using a non-linear functions. Each processing module maycomprise a plurality of inputs configured to receive a plurality of datainput values and perform a complex computing function. The combinedoutput OUT_(C1) may comprise the sum of each of the processing modules,e.g. the dot product of an input data vector with a respective weightvector. With a non-linear ANN architecture, the combined output OUT_(C1)is provided to a function unit where a non-linear transfer function isapplied to the combined output OUT_(C1). In such embodiments, the gainto be applied from correction module 1001 may be provided by adjusting areference waveform for the non-linear transfer function.

FIG. 11 illustrates a flow chart of a method of operating computingcircuitry according to an embodiment, where the computing circuitry hasan analogue computing unit and a voltage regulator for supplying avoltage to the analogue computing unit. The method involves the step1101 of operating the voltage regulator in a sequence of phases tocyclically regulate the first voltage supplied to the analoguecomputation unit. The method further comprises, the step 1102 of controloperation of the voltage regulator and/or operation of the analoguecomputation unit such that the analogue computation unit processes dataduring a plurality of compute periods that avoid times at which thevoltage regulator undergoes a phase transition which is one of apredefined set of phase transitions between defined phases in saidsequence of phases.

A circuit according to an embodiment of the present invention may beimplemented as an integrated circuit.

Computing circuitry according to the present embodiments may berelatively low power. Because of the ability for parallel processing ofdata without the need for multiple memory reads and memory writes thecomputing circuitry may be operable with relatively low latency, whichmay be particularly suitable for some applications, such as speech orspeaker recognition for example.

Embodiments of the present invention may be implemented in an electronicdevice, especially a portable and/or battery powered device, and inparticular may be implemented in a so-called edge device to enable edgecomputing. FIG. 12 illustrates an electronic device 1200 comprising acomputing circuit 200 such as described above. The electronic device maybe a portable or battery powered device, for instance a tablet or laptopcomputer, or smartphone or smartwatch or the like, or a communicationsinterface device such as a smart speaker or other smart listeningdevice. The device may, in some instance, be a voice controlled or voiceactivated device. The device could be a domestic appliance. The devicemay have a microphone 1201 and an ADC 1202. In some instances thecomputing circuit may be operable to process audio data received via themicrophone, e.g. for speech and/or speaker recognition. The device maycomprise an applications processor (AP) 1203 and in some implementationsthe computing circuitry may be operable to process data received fromthe AP and/or to provide data to the AP. In some instances the operationof the computing circuit 200 may be configured by the AP 1203 in use.The device may have at least one other user interface 1204, e.g. forallowing text input and in some applications the computing circuit 200may be operable to process data received via the UI 1004. The electronicdevice may also comprise an RF unit 1205 for sending and receiving datawirelessly, e.g. via WiFi™ or Bluetooth™. The computing circuitry 200may be operable to process data received via the RF unit 1205 and/or toprovide data to the RF unit 1005 for broadcast. In some embodimentsweight values to be stored in memory of the analogue computing circuitrymay be received or updated via the RF unit 1205.

The skilled person will recognise that some aspects of theabove-described apparatus and methods, for example the discovery andconfiguration methods may be embodied as processor control code, forexample on a non-volatile carrier medium such as a disk, CD- or DVD-ROM,programmed memory such as read only memory (Firmware), or on a datacarrier such as an optical or electrical signal carrier. For manyapplications, embodiments will be implemented on a DSP (Digital SignalProcessor), ASIC (Application Specific Integrated Circuit) or FPGA(Field Programmable Gate Array). Thus the code may comprise conventionalprogram code or microcode or, for example code for setting up orcontrolling an ASIC or FPGA. The code may also comprise code fordynamically configuring re-configurable apparatus such asre-programmable logic gate arrays. Similarly the code may comprise codefor a hardware description language such as Verilog™ or VHDL (Very highspeed integrated circuit Hardware Description Language). As the skilledperson will appreciate, the code may be distributed between a pluralityof coupled components in communication with one another. Whereappropriate, the embodiments may also be implemented using code runningon a field-(re)programmable analogue array or similar device in order toconfigure analogue hardware.

It should be noted that the above-mentioned embodiments illustraterather than limit the invention, and that those skilled in the art willbe able to design many alternative embodiments without departing fromthe scope of the appended claims. The word “comprising” does not excludethe presence of elements or steps other than those listed in the claim,“a” or “an” does not exclude a plurality, and a single feature or otherunit may fulfil the functions of several units recited in the claims.Any reference numerals or labels in the claims shall not be construed soas to limit their scope. Terms such as amplify or gain include possiblyapplying a scaling factor or less than unity to a signal.

As used herein, when two or more elements are referred to as “coupled”to one another, such term indicates that such two or more elements arein electronic communication or mechanical communication, as applicable,whether connected indirectly or directly, with or without interveningelements.

This disclosure encompasses all changes, substitutions, variations,alterations, and modifications to the example embodiments herein that aperson having ordinary skill in the art would comprehend. Similarly,where appropriate, the appended claims encompass all changes,substitutions, variations, alterations, and modifications to the exampleembodiments herein that a person having ordinary skill in the art wouldcomprehend. Moreover, reference in the appended claims to an apparatusor system or a component of an apparatus or system being adapted to,arranged to, capable of, configured to, enabled to, operable to, oroperative to perform a particular function encompasses that apparatus,system, or component, whether or not it or that particular function isactivated, turned on, or unlocked, as long as that apparatus, system, orcomponent is so adapted, arranged, capable, configured, enabled,operable, or operative. Accordingly, modifications, additions, oromissions may be made to the systems, apparatuses, and methods describedherein without departing from the scope of the disclosure. For example,the components of the systems and apparatuses may be integrated orseparated. Moreover, the operations of the systems and apparatusesdisclosed herein may be performed by more, fewer, or other componentsand the methods described may include more, fewer, or other steps.Additionally, steps may be performed in any suitable order. As used inthis document, “each” refers to each member of a set or each member of asubset of a set.

Although exemplary embodiments are illustrated in the figures anddescribed below, the principles of the present disclosure may beimplemented using any number of techniques, whether currently known ornot. The present disclosure should in no way be limited to the exemplaryimplementations and techniques illustrated in the drawings and describedabove.

Unless otherwise specifically noted, articles depicted in the drawingsare not necessarily drawn to scale.

All examples and conditional language recited herein are intended forpedagogical objects to aid the reader in understanding the disclosureand the concepts contributed by the inventor to furthering the art, andare construed as being without limitation to such specifically recitedexamples and conditions. Although embodiments of the present disclosurehave been described in detail, it should be understood that variouschanges, substitutions, and alterations could be made hereto withoutdeparting from the spirit and scope of the disclosure.

Although specific advantages have been enumerated above, variousembodiments may include some, none, or all of the enumerated advantages.Additionally, other technical advantages may become readily apparent toone of ordinary skill in the art after review of the foregoing figuresand description.

To aid the Patent Office and any readers of any patent issued on thisapplication in interpreting the claims appended hereto, applicants wishto note that they do not intend any of the appended claims or claimelements to invoke 35 U.S.C. § 112(f) unless the words “means for” or“step for” are explicitly used in the particular claim.

The invention claimed is:
 1. Computing circuitry, comprising: acomputation unit for processing data; a voltage regulator configured tosupply a first voltage to the computation unit and operable in asequence of phases to cyclically regulate the first voltage; and acontroller configured to control operation of the voltage regulatorand/or operation of the computation unit such that the computation unitprocesses data during a plurality of compute periods that avoid times atwhich the voltage regulator undergoes a phase transition.
 2. Thecomputing circuitry of claim 1 wherein the controller is configured tocontrol operation of the computation unit to suspend the computationunit from processing data during a period where the voltage regulator isundergoing a phase.
 3. The computing circuitry of claim 1 wherein thecontroller is configured to control operation of the computation unit tostart and end a compute period during at least one phase of the sequenceof phases.
 4. The computing circuitry of claim 3 wherein the controlleris configured to control operation of the computation unit to start andend a compute period during each one of the sequence of phases.
 5. Thecomputing circuitry of claim 3 wherein the controller is configured tocontrol operation of the computation unit so that there are no computeperiods when the voltage regulator is in at least one predefined phaseof said sequence of phases.
 6. The computing circuitry of claim 1wherein the controller is configured to control the voltage regulator soas to suspend the voltage regulator from undergoing a phase transitionso as to allow time for a compute period to be completed.
 7. Thecomputing circuitry of claim 6 wherein the computation unit isconfigured to provide a computation status to the controller indicativeof whether computing may be suspended and the controller is configuredto control operation of the voltage regulator based, at least partly, onthe computation status.
 8. The computing circuitry of claim 1 whereinthe voltage regulator is configured to provide a regulator status to thecontroller indicative that the voltage regulator is undergoing or isabout to undergo a phase transition in said predefined set of phasetransitions and the controller is configured to control the operation ofthe voltage regulator and/or the operation of the analogue computingunit based, at least partly, on said regulator status.
 9. The computingcircuitry of claim 1 wherein the controller comprises a clocking unitconfigured to supply a first clock reference signal to the voltageregulator to operate the voltage regulator to cycle through theplurality of phases and wherein the controller is configured to operatethe clocking unit to maintain the first clock reference signal at aconstant signal level to suspend the voltage regulator from undergoing aphase transition.
 10. The computing circuitry of claim 1 wherein thecontroller is configured to control the voltage regulator to operate ina first mode to cyclically regulate the first voltage and in a secondmode to suspend regulation of the first voltage; and wherein thecontroller is further configured to control the computing unit so thatat least some compute periods occur when the voltage regulator isoperating in the second mode.
 11. The computing circuitry of claim 10wherein the controller is configured to repeatedly control operation ofthe voltage regulator in the first mode during a plurality of first timeperiods interspersed with operation of the voltage regulator in thesecond mode during a plurality of second time periods.
 12. The computingcircuitry of claim 11 wherein the duration of at least one of the firsttime periods and the second time periods is variable.
 13. The computingcircuitry of claim 12 wherein, in the first mode of operation of thevoltage regulator, the controller is configured to compare an indicationof the magnitude of the first voltage to a first threshold and to switchto the second mode if the indication of the magnitude of the firstvoltage crosses the first threshold.
 14. The computing circuitry ofclaim 12 wherein, in the second mode of operation of the voltageregulator, the controller is configured to compare an indication of themagnitude of the first voltage to a second threshold and to switch tothe first mode if the indication of the magnitude of the first voltagecrosses the second threshold value.
 15. The computing circuitry of claim10 wherein the controller is configured to control the computing unitsuch that there is a first compute period during a period of operationof the voltage regulator in the second mode and a second compute periodduring a subsequent period of operation of the voltage regulator in thesecond mode, wherein the first and second compute periods areinterspersed with at least one period of operation of the voltageregulator in the first mode.
 16. Computing circuitry, comprising: acomputation unit for processing data; a voltage regulator configured tosupply a first voltage to the computation unit and operable in a firstmode in a cyclic sequence of phases to regulate the first voltage; and acontroller configured to control the analogue computation unit and/orthe voltage regulator so that data processing is performed during aperiod that does not include a phase transition of the voltage regulatorbetween different phases in said sequence of phases and that dataprocessing is suspended during any period that includes of such a phasetransition.
 17. Computing circuitry, comprising: a processor forprocessing data; a voltage regulator configured to supply a firstvoltage to the processor and operable in a sequence of phases tocyclically regulate the first voltage; and a controller configured tocontrol operation of the voltage regulator and/or operation of theprocessor such that the processor processes data during a plurality ofcompute periods that avoid times at which the voltage regulatorundergoes a phase transition.